1. Field of the Invention
This invention relates to a circuit for correcting data reading clock pulses, and more particularly to an improved circuit for correcting data reading clock pulses which is capable of eliminating mis-reading of data due to timing error of the data reading clock pulses.
2. Description of the Prior Art
In general, reading clock pulses are required to read n-bits of data within a period of time T and the timing of the pulses must be synchronized with an external signal. To this end, a synchronizing signal is generally required. Where no special synchronizing signal is provided for the data reading clock pulses, a start bit is formed, as dummy data, in the data to be read, so as to act as the desired synchronizing signal.
In the former case where a synchronizing signal per se is used, however, it is quite difficult to have the reading clock pulses coincide with the synchronizing signal when mass-produced digital circuits etc. are employed. This has been a problem to be solved. On the other hand, the latter case where a start bit is used has the disadvantage that an additional bit needs to be inserted in a limited time space and a time space for one data bit is reduced.